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general description the max17528 comprises 1-phase quick-pwm ? step- down vid power-supply controllers for intel notebookcpus. the quick-pwm control provides instantaneous response to fast-load current steps. active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. the max17528 is intended for two different notebook cpu/gpu core applications: either bucking down the bat- tery directly to create the core voltage, or bucking down the +5v system supply. the single-stage conversionmethod allows these devices to directly step down high- voltage batteries for the highest possible efficiency. alternatively, 2-stage conversion (stepping down the +5v system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. a slew-rate controller allows controlled transitions between vid codes. a thermistor-based temperature sensor provides programmable thermal protection. a current monitor provides an analog output current pro- portional to the processor load current. the max17528 implements both the intel imvp-6.5 cpu core specifications ( clken pullup to 3.3v), as well as the intel gmch graphics core specifications( clken = gnd). the max17528 is available in a 32-pin, 5mm x 5mm tqfn package. applications imvp-6.5 core power supplyintel gmch 2009 intel calpella platforms graphics core power supply voltage-positioned step-down converters 1-to-4 lithium-ion (li+)-cell battery-to-cpu core supply converters notebooks/desktops/servers features ? 1-phase quick-pwm controller ? ?.5% v out accuracy over line, load, and temperature ? 7-bit imvp-6.5 dac ? imvp-6.5 and gmch compliant ? active voltage positioning with adjustable gain ? accurate droop and current limit ? remote output and ground sense ? adjustable output-voltage slew rate ? power-good window comparator ? current monitor ? temperature comparator ? drives large synchronous rectifier fets ? 2v to 26v battery input range ? adjustable switching frequency (600khz max) ? undervoltage and thermal-fault protection ? soft-startup and soft-shutdown ? internal boost diode max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ________________________________________________________________ maxim integrated products 1 max17528 thin qfn 5mm x 5mm top view pad gnd 2930 28 27 1211 13 gnds csn csp slow skip 14 imon v dd pgndd6 bstd5 d4 12 vrhot 4567 23 24 22 20 19 18 time ilim d0gnd clken shdn fb dl 3 21 31 10 v cc pwrgd 32 9 ccv ton pgdin 26 15 d1 dh 25 16 d2 thrm d3 8 17 lx pin configuration ordering information 19-4723; rev 0; 7/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package MAX17528GTJ+ -40 o c to +105 o c 32 tqfn-ep* quick-pwm is a trademark of maxim integrated products, inc. downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(circuit of figure 1, v in = 12v, v dd = v cc = 5v, clken pullup to 3.3v with 1.9k ? , shdn = slow = ilim = pgdin = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25 c.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , v dd to gnd .....................................................-0.3v to +6v d0Cd6 to gnd..........................................................-0.3v to +6v csp, csn to gnd ....................................................-0.3v to +6v ilim, thrm, pgdin, vrhot , pwrgd to gnd .......-0.3v to +6v clken to gnd.........................................................-0.3v to +6v skip, slow to gnd.................................................-0.3v to +6v ccv, fb, imon, time to gnd ...................-0.3v to (v cc + 0.3v) shdn to gnd (note 1)...........................................-0.3v to +30v ton to gnd ...........................................................-0.3v to +30v gnds, pgnd to gnd ...........................................-0.3v to +0.3v dl to pgnd................................................-0.3v to (v dd + 0.3v) bst to gnd ............................................................-0.3v to +36v lx to bst..................................................................-6v to +0.3v bst to v dd .............................................................-0.3v to +30v dh to lx ....................................................-0.3v to (v bst + 0.3v) continuous power dissipation (32-pin, 5mm x 5mm tqfn) up to +70c ..............................................................1702mw derating above +70c ..........................................21.3mw/c operating temperature range .........................-40c to +105c junction temperature ......................................................+150c storage temperature range .............................-65c to +165c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units pwm controller input-voltage range v cc , v dd 4.5 5.5 v dac codes from 0.8125v to 1.5000v -0.5 +0.5 % dac codes from 0.3750v to 0.8000v -7 +7 dc output-voltage accuracy measured at fb with respect to gnds; includes load- regulation error (note 3) dac codes from 0v to 0.3625v -20 +20 mv boot voltage v boot imvp-6.5 ( clken pullup to 3.3v with 1.9k ) 1.094 1.100 1.106 v line regulation error v cc = 4.5v to 5.5v, v in = 4.5v to 26v 0.1 % gnds input range -200 +200 mv gnds gain a gnds v out / v gnds , -200mv v gnds +200mv 0.97 1.00 1.03 v/v gnds input bias current i gnds t a = +25c -2 +2 a time voltage v time v cc = 4.5v to 5.5v, i time = 28a (r time = 71.5k ) 1.985 2.000 2.015 v r time = 71.5k (12.5mv/s nominal) -10 +10 r time = 35.7k (25mv/s nominal) to 178k (5mv/s nominal) -15 +15 soft-start and soft-shutdown; r time = 35.7k (3.125mv/s nominal) to 178k (0.625mv/s nominal) -20 +20 time slew-rate accuracy slo = gnd, r time = 35.7k (12.5mv/s nominal) to 178k (2.5mv/s nominal) -20 +20 % note 1: shdn can be forced to 12v for the purpose of debugging prototype breadboards using the no-fault test mode, which dis- ables fault protection. downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units r ton = 96.75k 142 167 192 r ton = 200k 300 333 366 on-time t on v in = 12v, v fb = 1.2v (note 4) r ton = 303.25k 425 500 575 ns minimum off-time t off(min) measured at dh (note 4) 300 375 ns ton shutdown input current shdn = gnd, v in = 26v, v cc = v dd = 0v or 5v, t a = +25c 0.01 1 a bias currents quiescent supply current (v cc ) i cc measured at v cc , v skip = 5v, fb forced above the regulation point 1.5 3 ma quiescent supply current (v dd ) i dd measured at v dd , skip = gnd, fb forced above the regulation point, t a = +25c 0.02 1 a shutdown supply current (v cc ) measured at v cc , shdn = gnd 15 30 a shutdown supply current (v dd ) measured at v dd , shdn = gnd, t a = +25c 0.01 1 a fault protection output undervoltage-protection threshold v uvp measured at fb with respect to unloaded output voltage -450 -400 -350 mv output undervoltage propagation dela y t uvp fb forced 25mv below trip threshold 10 s imvp-6.5 clken startup delay (boot time period, clken pullup to 3.3v with 1.9k ) t boot imvp-6.5: clken pullup to 3.3v with 1.9k ; measured from the time when fb reaches the boot target voltage (note 3); the time needed for fb to reach this target voltage is based on the slew rate set by r time 20 60 100 s imvp-6.5: clken pullup to 3.3v with 1.9k ; measured at startup from the time when clken goes low 3 5 8 pwrgd startup delay gmch: clken = gnd; measured from the time when fb reaches the target voltage (note 3); the time needed for fb to reach this target voltage is based on the slew rate set by r time 3 5 8 ms lower threshold, falling edge (undervoltage) -350 -300 -250 pwrgd and clken (imvp-6.5, clken pullup to 3.3v with 1.9k ) threshold measured at fb with respect to unloaded output voltage, 15mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +200 +250 mv pwrgd and clken (imvp-6.5, clken pullup to 3.3v with 1.9k ) transition blanking time t blank measured from the time when fb reaches the target voltage (note 3) based on the slew rate set by r time 20 s pwrgd and clken (imvp-6.5, clken pullup to 3.3v with 1.9k ) delay fb forced 25mv outside the pwrgd trip thresholds 10 s electrical characteristics (continued)(circuit of figure 1, v in = 12v, v dd = v cc = 5v, clken pullup to 3.3v with 1.9k ? , shdn = slow = ilim = pgdin = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25 c.) (note 2) downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units imvp-6.5 clken output low voltage imvp-6.5: clken pullup to 3.3v with 1.9k ; i sink = 3ma 0.4 v imvp-6.5 clken high leakage current imvp-6.5: v pgdin = 5v, v clken = 3.3v 2 4 a imvp-6.5 clken shutdown leakage current imvp-6.5: v shdn = gnd, v clken = 3.3v 0.01 1 a pwrgd output low voltage i sink = 3ma 0.4 v pwrgd leakage current high state, pwrgd forced to 5v, t a = +25c 1 a v cc undervoltage lockout threshold v uvlo(vcc) rising edge, 65mv typical hysteresis, controller disabled below this level 4.05 4.27 4.48 v csn discharge resistance in uvlo and shutdown shdn = gnd and drivers disabled (not switching) 8 thermal protection vrhot trip threshold measured at thrm with respect to v cc ; falling edge; typical hysteresis = 100mv 29.2 30 30.8 % vrhot delay t vrhot thrm forced 25mv below the vrhot trip threshold; falling edge 10 s vrhot output on-resistance r vrhot low state 2 8 vrhot leakage current i vrhot high state, vrhot forced to 5v, t a = +25c 1 a thrm input leakage i thrm v thrm = 0v to 5v, t a = +25c -100 +100 na thermal-shutdown threshold t shdn typical hysteresis = 15c +160 c valley current limit and droop v time - v ilim = 100mv 7 10 13 current-limit threshold voltage (positive adjustable) v limit v csp - v csn v time - v ilim = 500mv 45 50 55 mv current-limit threshold voltage (positive default) preset v csp - v csn, ilim = v cc 20 22.5 25 mv current-limit threshold voltage (negative) accuracy v limit(neg) v csp - v csn , nominally -125% of v limit -4 +4 mv current-limit threshold voltage (zero crossing) v zero v pgnd - v lx , skip = v cc 1 mv csp, csn common-mode input range 0 2 v csp, csn input current t a = +25c -0.2 +0.2 a ilim input current t a = +25c -100 +100 na dc droop amplifier (gmd) offset (v csp - v csn ) at i fb = 0 -0.75 +0.75 mv dc droop amplifier (gmd) transconductance i fb / (v csp - v csn ); v fb = v csn = 0.45v to 2.0v, and (v csp - v csn ) = -15.0mv to +15.0mv 592 600 608 s electrical characteristics (continued)(circuit of figure 1, v in = 12v, v dd = v cc = 5v, clken pullup to 3.3v with 1.9k ? , shdn = slow = ilim = pgdin = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25 c.) (note 2) downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers _______________________________________________________________________________________ 5 electrical characteristics (continued)(circuit of figure 1, v in = 12v, v dd = v cc = 5v, clken pullup to 3.3v with 1.9k ? , shdn = slow = ilim = pgdin = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100). t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units gate drivers high state (pullup) 0.9 2.5 dh gate-driver on-resistance r on(dh) bst - lx forced to 5v low state (pulldown) 0.7 2.0 high state (pullup) 0.7 2.0 dl gate-driver on-resistance r on(dl) low state (pulldown) 0.25 0.7 dh gate-driver source current i dh(source) dh forced to 2.5v, bst - lx forced to 5v 2.2 a dh gate-driver sink current i dh(sink) dh forced to 2.5v, bst - lx forced to 5v 2.7 a dl gate-driver source current i dl(source) dl forced to 2.5v 2.7 a dl gate-driver sink current i dl(sink) dl forced to 2.5v 8 a dh low to dl high 20 driver propagation delay dl low to dh high 20 ns dl falling, c dl = 3nf 20 dl transition time dl rising, c dl = 3nf 20 ns dh falling, c dh = 3nf 20 dh transition time dh rising, c dh = 3nf 20 ns internal bst switch on-resistance r bst i bst = 10ma, v dd = 5v (note 6) 10 20 current monitor current-monitor transconductance g m(imon) i imon / (v csp - v csn ), v csn = 0.45v to 2.0v 4.9 5.0 5.1 ms current-monitor offset referred to v(csp, csn) i imon = 0 -1.0 +1.0 mv imon clamp voltage v imon i imon = -1ma 1.05 1.10 1.15 v logic and i/o logic-input high voltage v ih pgdin 2.3 v logic-input low voltage v il pgdin 1.0 v low-voltage logic- input high voltage v ihlv shdn , skip, slo , d0Cd6 0.67 v low-voltage logic- input low voltage v illv shdn , skip, slo , d0Cd6 0.33 v logic-input current pgdin ,shdn , skip, slo , d0Cd6 = 0 or 5v, t a = +25c -1 +1 a clken logic-input high voltage for imvp-6.5 startup 2.3 v clken logic-input low voltage for gmch 1.0 v downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 6 _______________________________________________________________________________________ electrical characteristics(circuit of figure 1, v in = 12v, v dd = v cc = 5v, clken pullup to 3.3v with 1.9k ? , shdn = slow = ilim = pgdin = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100). t a = -40? to +105? , unless other- wise specified.) (note 2) parameter symbol conditions min max units pwm controller input-voltage range v cc , v dd 4.5 5.5 v dac codes from 0.8125v to 1.5000v -0.75 +0.75 % dac codes from 0.3750v to 0.8000v -10 +10 dc output-voltage accuracy measured at fb with respect to gnds; includes load- regulation error (note 3) dac codes from 0v to 0.3625v -25 +25 mv boot voltage v boot imvp-6.5 ( clken pullup to 3.3v with 1.9k ) 1.085 1.115 v gnds input range -200 +200 mv gnds gain a gnds v out / v gnds , -200mv v gnds +200mv 0.95 1.05 v/v time voltage v time v cc = 4.5v to 5.5v, i time = 28a (r time = 71.5k ) 1.98 2.02 v r time = 71.5k (12.5mv/s nominal) -10 +10 r time = 35.7k (25mv/s nominal) to 178k (5mv/s nominal) -15 +15 soft-start and soft-shutdown; r time = 35.7k (3.125mv/s nominal) to 178k (0.625mv/s nominal) -20 +20 time slew-rate accuracy slo = gnd, r time = 35.7k (12.5mv/s nominal) to 178k (2.5mv/s nominal) -20 +20 % r ton = 96.75k 142 192 r ton = 200k 300 366 on-time t on v in = 12v, v fb = 1.2v (note 4) r ton = 303.25k 425 575 ns minimum off-time t off(min) measured at dh (note 4) 400 ns bias currents quiescent supply current (v cc ) i cc measured at v cc , v skip = 5v, fb forced above the regulation point 3 ma fault protection output undervoltage-protection threshold v uvp measured at fb with respect to unloaded output voltage -460 -340 mv imvp-6.5 clken startup delay (boot time period, clken pullup to 3.3v with 1.9k ) t boot imvp-6.5, clken pullup to 3.3v with 1.9k ; measured from the time when fb reaches the boot target voltage (note 3); the time needed for fb to reach this target voltage is based on the slew rate set by r time 20 100 s downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers _______________________________________________________________________________________ 7 electrical characteristics (continued)(circuit of figure 1, v in = 12v, v dd = v cc = 5v, clken pullup to 3.3v with 1.9k ? , shdn = slow = ilim = pgdin = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100). t a = -40? to +105? , unless other- wise specified.) (note 2) parameter symbol conditions min max units imvp-6.5, clken pullup to 3.3v with 1.9k ; measured at startup from the time when clken goes low 3 8 ms pwrgd startup delay gmch, clken = gnd; measured from the time when fb reaches the target voltage (note 3); the time needed for fb to reach this target voltage is based on the slew rate set by r time 3 8 s lower threshold, falling edge (undervoltage) -360 -240 pwrgd and clken (imvp-6.5, clken pullup to 3.3v with 1.9k ) threshold measured at fb with respect to unloaded output voltage, 15mv hysteresis (typ) upper threshold, rising edge (overvoltage) +140 +260 mv imvp-6.5 clken output low voltage imvp-6.5: clken pullup to 3.3v with 1.9k , i sink = 3ma 0.4 v imvp-6.5 clken high leakage current imvp-6.5 = pgdin = 5v, v clken = 3.3v 4 a pwrgd output low voltage i sink = 3ma 0.4 v v cc undervoltage lockout (uvlo) threshold v uvlo(vcc) rising edge, 65mv typical hysteresis, controller disabled below this level 4.0 4.5 v thermal protection vrhot trip threshold measured at thrm with respect to v cc ; falling edge; typical hysteresis = 100mv 29 31 % vrhot output on-resistance r vrhot low state 8 valley current limit and droop v time - v ilim = 100mv 7 13 current-limit threshold voltage (positive adjustable) v limit v csp - v csn v time - v ilim = 500mv 45 55 mv current-limit threshold voltage (positive default preset) v csp - v csn, ilim = v cc 20 25 mv current-limit threshold voltage (negative) accuracy v limit(neg) v csp - v csn , nominally -125% of v limit -5 +5 mv csp, csn common-mode input range 0 2 v dc droop amplifier (gmd) offset (v csp - v csn ) at i fb = 0 -1.0 +1.0 mv dc droop amplifier (gmd) transconductance i fb / (v csp - v csn ); fb = v csn = 0.45v to 2.0v, and (v csp - v csn ) = -15.0mv to +15.0mv 588 612 s downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 8 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 1, v in = 12v, v dd = v cc = 5v, clken pullup to 3.3v with 1.9k ? , shdn = slow = ilim = pgdin = v cc , skip = gnds = pgnd = gnd, v fb = v csp = v csn = 1.200v, d0Cd6 set for 1.20v (d0Cd6 = 0001100). t a = -40? to +105? , unless other- wise specified.) (note 2) parameter symbol conditions min typ max units gate drivers high state (pullup) 2.5 dh gate-driver on-resistance r on(dh) bst - lx forced to 5v low state (pulldown) 2.0 high state (pullup) 2.0 dl gate-driver on-resistance r on(dl) low state (pulldown) 0.7 internal bst switch on-resistance r bst i bst = 10ma, v dd = 5v 20 current monitor current-monitor transconductance g m(imon) i imon / (v csp - v csn ), v csn = 0.45v to 2.0v 4.9 5.1 ms current-monitor offset referred to v(csp, csn) i imon = 0 -1.5 +1.5 mv i mon clamp voltage v imon i imon = -1ma 1.05 1.15 v logic and i/o logic-input high voltage v ih pgdin 2.3 v logic-input low voltage v il pgdin 1.0 v low-voltage logic- input high voltage v ihlv shdn , skip, slo, d0Cd6 0.67 v low-voltage logic- input low voltage v illv shdn , skip, slo, d0Cd6 0.33 v clken logic-input high voltage for imvp-6.5 startup 2.3 v clken logic-input low voltage for gmch 1.0 v note 2: limits are 100% production tested at t a = +25c. maximum and minimum limits over temperature are guaranteed by design and characterization. note 3: the equation for the target voltage v target is: v target = the slew-rate-controlled version of v dac , where v dac = 0v for shutdown, v dac = v boot (imvp-6.5) or v vid (gmch) during startup, and v dac = v vid otherwise (the v vid voltages for all possible vid codes are given in table 2). in pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. note 4: on-time and minimum off-time specifications are measured from 50% to 50% at the dh pin, with lx forced to 0v, bst forced to 5v, and a 500pf capacitor from dh to lx to simulate external mosfet gate capacitance. actual in-circuit times can bedifferent due to mosfet switching speeds. downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers _______________________________________________________________________________________ 9 typical operating characteristics (t a = +25c, unless otherwise noted. circuit of figure 1.) 0.9v output efficiency vs. load current max17528 toc01 load current (a) efficiency (%) 10 1 0.1 60 70 80 90 100 50 0.01 100 12v 20v skip modepwm mode 7v 0.9v output voltage vs. load current max17528 toc02 load current (a) output voltage (v) 20 15 10 5 0.86 0.88 0.90 0.920.84 02 5 skip mode pwm mode 0.65v output efficiency vs. load current max17528 toc03 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 12v 20v 7v skip modepwm mode 0.65v output voltage vs. load current max17528 toc04 load current (a) output voltage (v) 8 6 4 2 0.640.63 0.65 0.66 0.670.62 01 0 skip mode pwm mode output efficiency vs. load current max17528 toc05 load current (a) efficiency (%) 1 0.1 60 70 80 90 100 50 0.01 10 12v 20v 7v skip modepwm mode output voltage vs. load current max17528 toc06 load current (a) output voltage (v) 8 6 4 2 1.02 1.061.04 1.00 1.08 1.10 1.120.98 01 0 skip mode pwm mode switching frequency vs. load current max17528 toc07 load current (a) switching frequency (khz) 10 1 0.1 100 200 300 400 500 0 150 250 350 450 50 0.01 100 v out = 0.9v v out = 0.65v skip modepwm mode switching frequency vs. load current max17528 toc08 input voltage (v) switching frequency (khz) 1 0.1 50 150100 200 250 300 0 0.01 10 skip mode pwm mode v out = 0.9v no-load supply current vs. input voltage max17528 toc09 input voltage (v) supply current (ma) 18 12 1 10 100 0.1 62 4 15 92 1 i cc + i dd (pwm) i cc + i dd (skip) i in (pwm) i in (skip) skip modepwm mode downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 10 ______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25c, unless otherwise noted. circuit of figure 1.) v out = 0.65v no-load supply current vs. input voltage max17528 toc10 input voltage (v) supply current (ma) 18 12 1 10 100 0.1 62 4 15 92 1 i cc + i dd (pwm) i cc + i dd (skip) i in (pwm) i in (skip) skip modepwm mode no-load supply current vs. input voltage max17528 toc11 input voltage (v) i bias (ma) 18 12 1 10 100 0.1 62 4 15 92 1 i cc + i dd (pwm) i cc + i dd (skip) i in (pwm) skip modepwm mode i in (skip) imon current and error vs. load current max17528 toc12 v csp-n (mv) error (%) imon ( a) 12 14 10 8 6 24 8 12 0 4 16 20 30 45 750 15 60 01 6 skippwm imon transconductance distribution max17528 toc13 imon transconductance (ms) percentage (%) 90 0 30 50 7040 10 20 60 80 4.904.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 sample size = 100 +85 c +25 c 0.8125v output voltage distribution max17528 toc14 output voltage (v) sample percentage (%) 70 0 40 50 6010 20 30 0.80750.8085 0.8095 0.8105 0.8115 0.8125 0.8135 0.8145 0.8155 0.8165 0.8175 sample size = 100 +85 c +25 c g m (fb) transconductance distribution max17528 toc15 transconductance ( s) sample percentage (%) 0 40 50 6010 20 30 590592 594 596 598 600 602 604 606 608 610 sample size = 100 +85 c +25 c downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 11 c. v out , 500mv/div d. inductor current, 10a/div imvp-6.5 soft-start waveform (up to clken) max17528 toc16 200 s/div a. shdn, 5v/divb. clken, 5v/div 0 5v 0 5v 0 1v 0 b ad c imvp-6.5 soft-start waveform (up to pwrgd) max17528 toc17 1ms/div a. shdn, 5v/divb. pwrgd, 5v/div c. clken, 5v/div d. v out , 500mv/div e. inductor current, 10a/div 0 5v5v 0 5v 0 1v 00 b ad e c imvp-6.5 shutdown waveform max17528 toc18 100 s/div a. shdn, 5v/divb. clken, 3.3v/div c. pwrgd, 5v/div e. dl, 5v/div d. v out , 1v/div f. inductor current, 5a/div 0 3.3v 5v 0 5v 0 0.9v 5v 00 b ad e f c gmch soft-start waveform max17528 toc19 1ms/div a. shdn, 5v/divb. pwrgd, 5v/div c. v out , 500mv/div d. inductor current, 10a/div 0 5v 0.9v 0 5v 0 0 b ad c gmch shutdown waveform max17528 toc20 100 s/div a. shdn, 5v/divb. pwrgd, 5v/div c. dl, 5v/div d. v out , 500mv/div e. inductor current, 5a/div 0 5v5v 1.0815v 0 5v 0 00 b ad e c load-transient response (imvp-6.5 hfm mode) max17528 toc21 20 s/div a. i out = 5.5a to 23a, 10a/div b. v out , 50mv/div c. inductor current, 10a/div 5.5a 5.5a0.9v 23a 23a 0.863v b ac typical operating characteristics (continued) (t a = +25c, unless otherwise noted. circuit of figure 1.) downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 12 ______________________________________________________________________________________ dprslpvr = high, slow = low, vid5 transition max17528 toc24 40 s/div a. vid5, 1v/divb. v out , 200mv/div i out = 1a c. inductor current, 10a/div 0 0 1v1v 0.6v b ac load-transient response (imvp-6.5 lfm mode) max17528 toc22 20 s/div a. i out = 3.5a to 9.5a, 5a/divb. v out , 20mv/div c. inductor current, 10a/div 3.5a 3.5a9.5a 9.5a 0.8375v 0.825v b ac load-transient response max17528 toc23 20 s/div a. i out = 1.5a to 8a, 5a/divb. v out , 50mv/div c. inductor current, 5a/div 1.5a 1.5a 8a 8a 1.0815v 1.03v b ac typical operating characteristics (continued) (t a = +25c, unless otherwise noted. circuit of figure 1.) dprslpvr = high, slow = high, vid5 transition max17528 toc25 40 s/div a. vid5, 1v/divb. v out , 200mv/div i out = 1a c. inductor current, 10a/div 0 0 1v1v 0.6v b ac d0 12.5mv dynamic vid code change max17528 toc26 10 s/div a. d0, 5v/divb. v out , 20mv/div c. inductor current, 2a/div 0 0 5v 0.9v 0.8875v b ac d2 50mv dynamic vid code change max17528 toc27 10 s/div a. d2, 5v/divb. v out , 50mv/div c. inductor current, 2a/div 0 0 5v 0.9v 0.85v b ac downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 13 output overload waveform max17528 toc28 100 s/div a. v out , 500mv/div b. pgood, 5v/div c. dl, 5v/divd. inductor current, 10a/div 0 00 1v5v 5v 0 b ac d bias supply removal (uvlo response) max17528 toc29 200 s/div a. 5v bias supply, 5v/divb. v out , 500mv/div c. dl, 5v/div d. pgood, 5v/dive. inductor current, 10a/div 0 0 5v 0.9v 5v 00 5v 10a b ac d e typical operating characteristics (continued) (t a = +25c, unless otherwise noted. circuit of figure 1.) downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 14 ______________________________________________________________________________________ pin description pin name function 1 imon current monitor output. the max17528 imon output sources a current that is directly proportional to the current-sense voltage as defined by: i imon = g m(imon) x (v csp - v csn ) where g m(imon) = 5ms (typ). the imon current is unidirectional (sources current out of imon only) for positive current-sense values. for negative current-sense voltages, the imon current is zero. connect an external resistor between imon and vss_sense to create the des ired imon gain based on the following equation: r imon = 0.999v/(imax x r sense x g m(imon) ) where imax is defined in the crrent monitor (imon) section of the intel imvp-6.5 specification and based on discrete increments (20a, 30a, 40a, etc.,), r sense is the typical effective value of the current-sense element (sense resistor or inductor dcr) that is us ed to provide the current-sense voltage, and g m(imon) is the typical transconductance amplifier gain as defined in the electrical characteristics table. the imon voltage is internally clamped to a maximum of 1.1v (typ). the transconductance amplifier and voltage clamp are internally compe nsated, so imon cannot directly drive large capacitance values. to filter the imon sign al, use an rc filter as shown in figure 1. imon is pulled to ground when the max17528 is in shutdo wn. 2 gnds remote ground-sense input. connect directly to the cpu or gmch v ss sense pin (ground sense) or directly to the ground connection of the load. gnds internally connects to a transconductance amplifier that adjusts the feedback voltage, compensating for vo ltage drops between the regulators ground and the processors ground. 3 fb output of the voltage-positioning transconductance amplifier. conn ect a resistor, r fb , between fb and the positive side of the feedback remote sense to set the s teady-state droop based on the voltage-positioning gain requirement. r fb = r droop /(r sense x gmd) where r droop is the desired voltage-positioning slope, gmd = 600s typ and r sense is the value of the current-sense resistor that is used to provide the (cs p, csn), current-sense voltage. if lossless sensing is used, r sense = r l . in this case, consider using a thermistor-resistor network to minimize the temperature dependence of the voltage-positioning slop e. droop can be disabled by shorting fb to the positive remote-sense point, but doing so i ncreases the minimum esr requirement of the output capacitance for stability, and fb might therefo re need to be driven by a carefully designed feed-forward network. fb is high impedance in shut down. 4 csn negative inductor current-sense input. connect csn to the negative term inal of the inductor current-sensing resistor or directly to the negative terminal of th e inductor if the lossless dcr sensing method is used (see figure 4). under v cc uvlo conditions and after soft-shutdown is completed, csn is internal ly pulled to gnd through a 10 fet to discharge the output. 5 csp positive inductor current-sense input. connect csp to the positive term inal of the inductor current- sensing resistor or directly to the positive terminal of the fi ltering capacitor used when the lossless dcr sensing method is used (see figure 4). 6 slo active-low slew-rate select input. this 1.0v logic input signal s elects between the nominal and slow (half of nominal rate) slew rates. when slo is forced high, the selected nominal slew rate is set by the time resistance. when slo is forced low, the slew rate is reduced to half of the nominal slew rate. for imvp-6.5 applications ( clken pullup to 3.3v with 1.9k ), the fast slew rate is not needed. connect slo to gnd. for gmch 2009 applications ( clken = gnd), connect to the system gfxdprslpvr signal. downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 15 pin description (continued) pin name function 7 skip pulse-skipping control input. this 1.0v logic input signal indicates power usage and sets the operating mode of the max17528. when skip is forced high, the controller is immediately set to automatic pulse-skipping mode. the controller returns to forced-pwm mode when skip is forced l ow and the output is in regulation. the pwrgd upper threshold is blanked during any downward output- voltage transition that happens when the controller is in skip mode, and stays blanked until the transition-related pwrgd blanking period is complete and the output reaches regul ation. imvp-6.5: the max17528 is in skip mode during startup and while in boot mode, but is in for ced-pwm mode during the transition from boot mode to vid mode plus 20s, and during soft-shutdow n, irrespective of the skip logic level. connect to the system dprslpvr signal. gmch 2009: the max17528 is in skip mode during startup, while in standby mode, and while exiting standby mode, but is in forced-pwm mode during soft-shutdown, and while entering s tandby mode, irrespective of the skip logic level. connect to the system gfxdprslpvr sign al. 8 thrm comparator input for thermal protection. thrm connects to the positive input of an internal comparator. the comparators negative input connects to an internal resist ive voltage-divider that accurately sets the thrm threshold to 30% of the v cc voltage. connect the output of a resistor and thermistor-divider (between v cc and gnd) to thrm with the values selected so the voltage at thrm falls below 30% of v cc (1.5v when v cc = 5v) at the desired high temperature. 9 ton switching frequency setting input. an external resistor between the input po wer source and this pin sets the switching period (t sw = 1/f sw ) according to the following equation: t sw = 16.3pf x (r ton + 6.5k ) ton becomes high impedance in shutdown to reduce the input qui escent current. if the ton current is less than 10a, the max17528 disables the controller, sets the ton open fault latch, and pulls dl and dh low. 10 pwrgd open-drain power-good output. pwrgd is high impedance after output-v oltage transitions (except during power-up and power-down) if fb is in regulation. during startup, pwrgd is held low. imvp-6.5: pwrgd continues to be low while the output is at the boot voltage, and stays low until 5ms (typ) after clken goes low. gmch 2009: pwrgd starts monitoring the fb voltage 5ms (typ) after startup (from shutdown or standby mode) is complete. pwrgd is also held low while in standby mode, and while entering and exiting standby mode. pwrgd is forced low during soft-shutdown and while in shutdown. pwrgd is forced high impedance whenever the slew-rate controller is active (output -voltage transitions), and continues to be forced high impedance for an additional 20s after the transition i s completed. the pwrgd upper threshold is blanked during any downward output-voltag e transition that happens when the max17528 is in skip mode, and stays blanked until t he transition-related pwrgd blanking period is complete and the output reaches regula tion. a pullup resistor on pwrgd causes additional finite shutdown curr ent. 11 shdn active-low shutdown control input. connect to v cc for normal operation. connect to ground to put the controller into the low-power 1a (max) shutdown state. during startup, the controller ramps up the output voltage at 1/8 the slew rate set by the time resistor to the target vo ltage defined by the application circuit: for imvp-6.5 ( clken pullup to 3.3v with 1.9k ), the startup target is the 1.1v boot voltage. for gmch 2009 ( clken = gnd), the startup target is the voltage set by the vid inputs. during the shutdown transition, the max17528 softly ramps down th e output voltage at 1/8 the slew rate set by the time resistor. forcing shdn to 11v~13v disables uvp, thermal shutdown, and clears the fault latches. downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 16 ______________________________________________________________________________________ pin description (continued) pin name function 12 clken dual-function gmch/imvp-6.5 select input and active-low imvp-6.5 cpu clock enable open- drain output. connect to system 3.3v supply through pullup re sistors for proper imvp-6.5 operation. clken voltage has to be higher than 2.3v before shdn is pulled high. connect to gnd to select the intel gmch feature set. this active-low logic output in dicates when the feedback voltage is in regulation. the max17528 forces clken low during dynamic vid transitions and for an additional 20s after the vid transition is completed. clken is the inverse of pwrgd, except for the 5ms pwrgd startup delay period after clken is pulled low. see the startup timing diagram (figure 9). the clken upper threshold is blanked during any downward output-voltage transit ion that happens when the max17528 are in skip mode, and stays blanked until the transition-related pwrgd blanking period is complete and the output reaches regula tion. 13 gnd analog ground 14C20 d0Cd6 low-voltage (1.0v logic) vid dac code inputs. the d0Cd6 inputs do no t have internal pullups. these 1.0v logic inputs are designed to interface directly with the cp u. the output voltage is set by the vid code indicated by the logic-level voltages on d0Cd6 ( see table 2). the 1111111 code corresponds to standby mode. when this code is detect ed, the max17528 enters standby mode while in forced-pwm mode, and slews to 0v at 1/8 the slew rate set by the time resistor. after slewing to 0v, the ic enters skip mode ( dh and dl low). if d6Cd0 is changed from 1111111 to a different code, the max17528 exits standby mode (while in skip mode) and slews the output voltage to the target voltage set by the vid code at 1x the s lew rate set by the time resistor. note that the standby supply current consumed by the max17528 is the same as its quiescent supply current, because no analog blocks are turned o ff. this is n ecessary because of the fast wake-up requirement. 21 pgnd power ground. ground connection for the dl driver. also used as an input to the max17528s zero- crossing comparator. 22 dl low-side gate-driver output. dl swings from pgnd to v dd . dl is forced low after shutdown. dl is forced low in skip mode after detecting an inductor current zero-crossing. 23 v dd supply voltage input for the dl driver. v dd is also the supply voltage used to internally recharge the bst flying capacitor during the time dl is high. connect v dd to the 4.5v to 5.5v system supply voltage. bypass v dd to pgnd with a 1f or greater ceramic capacitor. 24 bst boost flying capacitor connection. bst provides the upper supply ra il for the dh high-side gate driver. an internal switch between v dd and bst charges the flying capacitor while the low-side mosfet is on (dl pulled high and lx pulled to ground). 25 lx inductor connection. lx is the internal lower supply rail for the dh high-sid e gate driver. also used as an input to the max17528s zero-crossing comparator. 26 dh high-side gate-driver output. dh swings from lx to bst. the controller pull s dh low in shutdown. 27 pgdin imvp-6.5 power-good logic input. pgdin indicates the powe r status of other system rails used to power the chipset and cpu v ccp supplies. for the imvp-6.5 ( clken pullup to 3.3v with 1.9k ), the max17528 powers up and remains at the boot voltage (v boot ) as long as pgdin remains low. when pgdin is forced high, the max17528 transitions the output to the volt age set by the vid code, and clken is allowed to go low. if pgdin is pulled low at any time, the max17528 immediately forces clken high and pwrgd low and sets the output to the boot voltage. the output remai ns at the boot voltage until the system either disables the controller or until pgdin goes high again. for gmch 2009 applications ( clken = gnd), connect pgdin to the 5v bias supply. downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 17 pin description (continued) pin name function 28 vrhot active-low open-drain output of internal comparator. vrhot is pulled low when the voltage at thrm goes below 1.5v (30% of v cc ). vrhot is high-impedance in shutdown. 29 time slew-rate adjustment pin. time regulates to 2.0v and the load current determines the slew rate of the internal error-amplifier target. the sum of the resistance betwee n time and gnd (r time ) determines the nominal slew rate: slew rate = (12.5mv/s) x (71.5k /r time ) the guaranteed r time range is between 35.7k and 178k . this nominal slew rate applies to vid transitions and to the transition from boot mode to vid. if the vid dac inputs are clock ed, the slew rate for all other vid transitions is set by the rate at which they are clocked, up to a maxi mum slew rate equal to the nominal slew rate defined above. the startup and shutdown slew rates are always 1/8 of nominal slew rate to minimize surg e currents. if slo is high, the slew rate is reduced to 1/2 of nominal. 30 ilim valley current-limit adjustment input. the valley current-limit threshold voltage at csp to csn equals precisely 1/10 the differential time to ilim voltage over a 0.1v to 0.5v range (10mv to 50mv current-sense range). the negative current-limit threshold is nominally - 125% of the corresponding valley current-limit threshold. connect ilim directly to v cc to set the default current-limit threshold setting of 22.5mv (typ) nominal. 31 v cc controller supply voltage. connect to a 4.5v to 5.5v source. bypass to gnd with 1f minimum. 32 ccv integrator capacitor connection. connect a capacitor (c ccv ) from ccv to gnd to set the integration time constant. choose the capacitor value according to: 16 x (c ccv /g m(ccv) ) x f sw >> 1 where g m(ccv) = 320s (max) is the integrators transconductance and f sw is the switching frequency set by the r ton value. the integrator is internally disabled during any downward output-voltag e transition that occurs in pulse-skipping mode, and remains disabled until the transition bl anking period expires and the output reaches regulation (error amplifier transition detected). ep (gnd) exposed pad (back side) and analog ground. internally connected to gnd. connect to the gr ound plane through a thermally enhanced via. downloaded from: http:///
pwrgd v cc v dd shdn on off time gnds r pwrgd 10k ? r thrm 7.87k ? ntc2 100k ? b = 4700 3.3v (vron) r2 5.90k ? l1 0.36 h 0.8m ? n lo n hi c out lx dh dl bst pgnd csp csn imon r3 1k ? ton fb v cc cpu imon vss_sense c8 0.022 f 10 1 29 8 9 3 2 4 5 3123 22 21 25 26 24 11 d1 r101.00k ? r12 10k ? r11 1.50k ? ntc1 10k ? b = 4500 thrm vcc_sense vss_sense load-line adjustment: r fb = r droop /(r sense x 600 s) dcr thermal compensation pwr pwr pwr agnd ilim 30 r3 64.9k ? valley current limit set by time to ilim v limit = 0.2v x r2/(r2 + r3) slew rate set by time bias current dv/dt = 12.5mv/ s x 71.5k ? /(r2 + r3) core output gnd agnd slow 6 skip 7 clken 12 ccv 32 gnd 13 agnd agndagnd pgdin 27 d0d1 d2 d3 d4 agnd 1415 16 17 18 d5 19 d6 20 vrhot 28 remote-senseinputs remote-sense filters switching frequency (f sw = 1/t sw ): t sw = 16.3pf x (r ton + 6.5k ? ) r1610 ? r1510 ? catch resistors required when cpu not populated agnd r gnd 0 ? c ccv 100pf c9 1000pf r fb 4.53k ? 1% r13 10 ? pwr ep r4 13.0k ? system i/o power-good c in pwr max17528 agnd pwr r vrhot 10k ? 1.9k ? agnd c csp open c bst 0.1 f r bst 0 ? r ton 200k ? agnd c11.0 f c2 1.0 f r1 10 ? c sense 0.47 f agnd c csn open c10 1000pf r14 10 ? input 7v to 24v 5v bias input figure 1. imvp-6.5 cpu core application circuit max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 18 ______________________________________________________________________________________ downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 19 design parameters auburndale imvp-6.5 ulv auburndale imvp-6.5 ulv auburndale render gmch sv auburndale render gmch ulv circuit figure 1 figure 1 figure 2 figure 2 input-voltage range 7v to 20v 5v 7v to 20v 7v to 20v maximum load current (tdc current) 20a (15a) 20a (15a) 15a (10a) 7a (5a) transient load current 14a (10a/s) 14a (10a/s) 12a (10a/s) 5a (10a/s) load line 3mv/a 3mv/a 7mv/a 7mv/a poc setting 20a 20a 20a 20a components ton resistance (r ton ) 200k (f sw = 300khz) 120k (f sw = 500khz) 200k (f sw = 300khz) 200k (f sw = 300khz) inductance (l) nec/tokin mpc1055lr36 0.36h, 32a, 0.8m nec/tokin mpc1055lr36 0.36h, 32a, 0.8m nec/tokin mpcg0740lr42 0.42h, 20a, 1.55m nec/tokin mpc1040lr88c 0.88h, 24a, 2.3m high-side mosfet (n h ) siliconix 1x si4386dy 7.8m /9.5m (typ/max) siliconix 1x si4386dy 7.8m /9.5m (typ/max) siliconix 1x si4386dy 7.8m /9.5m (typ/max) siliconix 1x si4386dy 7.8m /9.5m (typ/max) low-side mosfet (n l ) siliconix 2x si4642dy 3.9m /4.7m (typ/max) siliconix 2x si4642dy 3.9m /4.7m (typ/max) siliconix 1x si4642dy 3.9m /4.7m (typ/max) siliconix 1x si4642dy 3.9m /4.7m (typ/max) output capacitors (c out ) 4x 330f, 6m , 2.5v panasonic eefsx0d0d331xr 32x 10f, 6v ceramic (0805) 4x 330f, 6m , 2.5v panasonic eefsx0d0d331xr 32x 10f, 6v ceramic (0805) 1x 470f, 6m , 2.5v sanyo 2r5tpd470m6l 10x 10f, 6v ceramic (0805) 1x 220f, 7m , 2v sanyo 2tpf220m7l 10x 10f, 6v ceramic (0805) input capacitors (c in ) 4x 10f, 25v ceramic (1210) 6x 10f, 6v ceramic (0805) 2x 10f, 25v ceramic (1210) 2x 10f, 25v ceramic (1210) time-ilim resistance (r1) 5.90k 5.90k 6.65k 6.65k ilim-gnd resistance (r2) 64.9k 64.9k 64.9k 64.9k fb resistance (r fb ) 4.53k 4.53k 10.0k 5.62k imon resistance (r4) 13.0k 13.0k 7.68k 4.42k lx-csp resistance (r5) 1.00k 1.00k 1.50k 0.806k csp-csn series resistance (r6) 1.50k 1.50k 1.50k 1.20k parallel ntc resistance (r7) 10.0k 10.0k 4.02k 15.0k dcr sense ntc (ntc1) 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f dcr sense capacitance (c sense ) 0.47f, 6v ceramic (0805) 0.47f, 6v ceramic (0805) 0.22f, 6v ceramic (0805) 0.47f, 6v ceramic (0805) table 1. imvp-6.5 component selection downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 20 ______________________________________________________________________________________ pwrgd v cc v dd shdn on off time gnds r pwrgd 10k ? r thrm 7.87k ? ntc2 100k ? b = 4700 3.3v (vron) r2 6.65k ? l1 0.42 h 1.55m ? n lo n hi c out lx dh dl bst pgnd csp csn imon r3 6.2k ? ton fb v cc gfx imon vssgfx_sense c8 0.022 f 10 1 29 8 9 3 2 4 5 3123 22 21 25 26 24 11 d1 r101.50k ? r12 4.02k ? r11 1.50k ? ntc1 10k ? b = 4500 thrm vccgfx_sense vssgfx_sense load-line adjustment: r fb = r droop /(r sense x 600 s) dcr thermal compensation pwr pwr pwr agnd ilim 30 r3 64.9k ? valley current limit set by time to ilim v limit = 0.2v x r2/(r2 + r3) slew rate set by time bias current dv/dt = 12.5mv/ s x 71.5k ? /(r2 + r3) gfx output gnd agnd slow 6 skip 7 clken 12 ccv 32 gnd 13 agnd agndagnd pgdin 27 d0d1 d2 d3 d4 vid inputs 1415 16 17 18 d5 19 d6 20 vrhot 28 remote-senseinputs remote-sense filters switching frequency (f sw = 1/t sw ): t sw = 16.3pf x (r ton + 6.5k ? ) r1610 ? r1510 ? catch resistors required when cpu not populated agnd r gnd 0 ? c ccv 100pf c9 1000pf r fb 10.0k ? 1% r13 10 ? pwr ep r4 7.68k ? c in pwr max17528 agnd pwr r vrhot 10k ? agnd c csp open c bst 0.1 f r bst 0 ? r ton 200k ? agnd c11.0 f c2 1.0 f r1 10 ? c sense 0.22 f agnd c csn open c10 1000pf r14 10 ? input 7v to 24v 5v bias input figure 2. gmch (render core) application circuit downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 21 detailed description free-running, constant on-time controllers with input feed-forward the quick-pwm control architecture is a pseudo-fixed-frequency, constant-on-time, current-mode regulator with voltage feed-forward (figure 3). this architecture relies on the output filter capacitors esr and the load regulation to provide the proper current-mode compen- sation, so the resulting feedback ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage, and directly proportional to the feedback volt- age (see the on-time one-shot section). another one- shot sets a minimum off-time. the on-time one-shottriggers when the error comparator goes low (the feed- back voltage drops below the target voltage), the inductor current is below the valley current-limit thresh- old, and the minimum off-time one-shot times out. +5v bias supply (v cc and v dd ) the quick-pwm controller requires an external +5v biassupply in addition to the battery. typically, this +5v bias supply is the notebooks 95%-efficient, +5v system sup- ply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v bias supply can be gen- erated with an external linear regulator. the +5v bias supply must provide v cc (pwm con- troller) and v dd (gate-drive power), so the maximum current drawn is:where i cc is provided in the electrical characteristics table, f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheets total gate- charge specification limits at v gs = 5v. v in and v dd can be connected if the input power source is a fixed +4.5v to +5.5v supply. if the +5v bias supply ispowered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensure startup. switching frequency (ton) connect a resistor (r ton ) between ton and v in to set the switching period (t sw = 1/f sw ): t sw = 16.3pf x (r ton + 6.5k ? ) a 96.75k ? to 303.25k ? corresponds to switching peri- ods of 1.67s (600khz) to 5s (200khz), respectively.high-frequency (over 500khz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low-frequency (under 300khz) operation offers the best overall efficiency at the expense of component size and board space. ton open-circuit fault protection the ton input includes open-circuit protection to avoidlong, uncontrolled on-times that could result in an over- voltage condition on the output. the max17528 detects an open-circuit fault if the ton current drops below 10a for any reasonthe ton resistor (r ton ) is unpopulated, a high resistance value is used, the inputvoltage is low, etc. under these conditions, the max17528 stops switching (dh and dl pulled low) and immediately sets the fault latch. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. on-time one-shot the core contains a fast, low-jitter, adjustable one-shotthat sets the high-side mosfets on-time. the one-shot varies the on-time in response to the input and feedback voltages. the main high-side switch on-time is inversely proportional to the input voltage as measured by the r ton input, and proportional to the feedback voltage (v fb ): where the switching period (t sw = 1/f sw ) is set by the resistor between v in and ton. this algorithm results in a nearly constant switching fre-quency despite the lack of a fixed-frequency clock generator. the benefits of a constant switching fre- quency are twofold: first, the frequency can be select- ed to avoid noise-sensitive regions, such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. the on-time one-shots have good accuracy at the operating points specified in the electrical characteristics table. on-times at operating points far removed from the conditions specified in the electrical characteristics table can vary over a wider range. tt v v on sw fb in = ? ? ? ? ? ? iifq q bias cc sw g low g high =+ + () () ( ) downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 22 ______________________________________________________________________________________ sr q rs q trig q one-shot pgnd dl bst dh lx ccv ref ton csp csn minimum off-time pwrgd target + 200mv target - 300mv target + 300mv target - 400mv shdn trig q one-shot on-time mode control fb slow skip v dd fb pgnd lx 1mv skip cspcsn d0?6 clken gnds 60 s startup delay 5ms startup delay dac current scaling time fault target ref ilim r fault blank v cc gnd ref (2.0v) 500k ? g m(ccv) 160 s g m(fb) 600 s g m(gnds) slew_rate pgdin imon g m(imon) 5ms currentmonitor vrhot thrm 0.3 x v cc max17528 10x figure 3. functional diagram downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 23 on-times translate only roughly to switching frequen-cies. the on-times guaranteed in the electrical characteristics table are influenced by switching delays in the external high-side mosfet. resistivelosses, including the inductor, both mosfets, and printed-circuit board (pcb) copper losses in the output and ground tend to raise the switching frequency as the load current increases. under light-load conditions, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only during forced-pwm operation and dynamic output-voltage transitions when the inductor current reverses at light- or negative-load currents. with reversed inductor cur- rent, the inductors emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: where v dis is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rec-tifier, inductor, and pcb resistances; v chg is the sum of the parasitic voltage drops in the inductor charge path,including high-side switch, inductor, and pcb resis- tances; and t on is the on-time as determined above. current sense the output current is differentially sensed by the high-impedance current-sense inputs (csp and csn). low- offset amplifiers are used for voltage-positioning gain, current-limit protection, and current monitoring. sensing the current at the output offers advantages, including less noise sensitivity and the flexibility to use either a current- sense resistor or the dc resistance of the power inductor. using the dc resistance (r dcr ) of the inductor allows higher efficiency. in this configuration, the initial toler-ance and temperature coefficient of the inductors dcr must be accounted for in the output-voltage droop- error budget and current monitor. this current-sense method uses an rc filtering network to extract the cur- rent information from the inductor (see figure 4). the resistive divider used should provide a current-sense resistance (r cs ) low enough to meet the current-limit requirements (r cs x i out(max) < 50mv), and the time constant of the rc network should match the inductorstime constant (l/r dcr ): and:where r cs is the required current-sense resistance, and r dcr is the inductors series dc resistance. use the worst-case inductance and r dcr values provided by the inductor manufacturer, adding some margin for theinductance drop over temperature and load. to mini- mize the current-sense error due to the current-sense inputs bias current (i csp ), choose r1 || r2 to be less than 2k ? and use the above equation to determine the sense capacitance (c eq ). choose capacitors with 5% tolerance and resistors with 1% tolerance specifications.temperature compensation is recommended for this current-sense method. see the voltage positioning and loop compensation section for detailed information. when using a current-sense resistor for accurate output-voltage positioning, the circuit requires a differential rc filter to eliminate the ac voltage step caused by the equivalent series inductance (l esl ) of the current-sense resistor (see figure 4). the esl-induced voltage stepdoes not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. similar to the inductor dcr sensing method, the rc filters time con- stant should match the l/r time constant formed by the current-sense resistors parasitic inductance: where l esl is the equivalent series inductance of the current-sense resistor, r sense is the current-sense resistance value, c eq and r1 are the time-constant matching components. l r cr esl sense eq = 1 r l crr dcr eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + ? ? ? ? ? ? 2 12 f vv tvv v sw out dis on in dis chg = + () + () downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 24 ______________________________________________________________________________________ current limit the current-limit circuit employs a valley current-sens-ing algorithm that uses a current-sense element (see figure 4) between the current-sense inputs (csp to csn) to detect the inductor current. if the differential current-sense voltage exceeds the current-limit thresh- old, the pwm controller does not initiate a new cycle until the inductor current drops below the valley current- limit threshold. since only the valley current level is actively limited, the actual peak inductor current exceeds the valley current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense impedance, inductor value, and battery voltage. when combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. the positive valley current-limit threshold voltage atcsp to csn equals precisely 1/10 of the differential time to ilim voltage over a 0.1v to 0.5v range (10mv to 50mv current-sense range). connect ilim directly to v cc to set the default current-limit threshold setting of 22.5mv nominal.the negative current-limit threshold (forced-pwm mode only) is nominally -125% of the corresponding valley current-limit threshold. when the inductor current drops below the negative current limit, the controller immedi- ately activates an on-time pulsedl turns off, and dh turns onallowing the inductor current to remain above the negative current threshold. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signals seen by the current-sense inputs (csp, csn). a) output series resistor sensing dh input (v in ) dl lx pgnd n h c in l esl r sense r sense l sense c eq c out c eq r1 = d l csp csn l sense resistor r1 r1 + r2 r2 r cs = ( ) [ + ] r dcr c eq l r dcr = r1 1 r2 1 for thermal compensation: r2 should consist of an ntc resistor in series with a standard thin-film resistor. n l b) lossless inductor sensing dh input (v in ) dl lx pgnd n h c in l dcr c eq c out d l csp csn inductor r1 n l r2 max17528 max17528 figure 4. current-sense methods downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 25 feedback the nominal no-load output voltage (v target ) is defined by the vid-selected dac voltage (see table 2)plus the remote ground-sense adjustment (v gnds ) as defined in the following equation:where v dac is the selected vid voltage. on startup, imvp-6.5 ( clken pullup to 3.3v with 1.9k ? ) applica- tions slew the target voltage from ground to the preset1.1v boot voltage and gmch ( clken = gnd) applica- tions slew the target voltage directly to the vid-selecteddac target. voltage-positioning amplifier (steady-state droop) the max17528 includes a transconductance amplifierfor adding gain to the voltage-positioning sense path. the amplifiers input is generated by the differential current-sense inputs that sense the inductor current by measuring the voltage across either current-sense resistors or the inductors dcr. the amplifiers output connects directly to the regulators voltage-positioned feedback input (fb), so the resistance between fb and the output-voltage sense point determines the voltage- positioning gain: where the target voltage (v target = v fb ) is defined by the selected vid code (table 3 for imvp6 or table 4 forgmch), and the fb amplifiers output current (i fb ) is determined by the sum of the current-sense voltages:where g m(fb) is typically 600s as defined in the electrical characteristics table. differential remote sense the max17528 includes differential, remote-senseinputs to eliminate the effects of voltage drops along the pcb traces and through the processors power pins. the feedback-sense node connects to the voltage-posi- tioning resistor (r fb ). the ground-sense (gnds) input connects to an amplifier that adds an offset directly tothe feedback voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. connect the voltage-positioning resistor (r fb ) and ground-sense (gnds) input directly to the processorsremote-sense outputs as shown in figures 1 and 2. integrator amplifier an integrator amplifier forces the dc average of the fbvoltage to equal the target voltage. this transconduc- tance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (figure 3), allowing accurate dc output-voltage regula- tion regardless of the output ripple voltage. the integra- tor amplifier has the ability to shift the output voltage by 50mv (typ). the integration time constant can be set easily with an external compensation capacitor between ccv and analog ground, with the minimum recommended ccv capacitor value determined by: c ccv >> g m(ccv) /(16 x f sw ) where g m(ccv) = 320s (max) is the integrators transconductance and f sw is the switching frequency set by the r ton resistance. the max17528 disables the integrator by connectingthe amplifier inputs together at the beginning of all downward vid transitions done in pulse-skipping mode (skip = high). the integrator remains disabled until 20s after the transition is completed (the internal tar- get settles) and the output is in regulation (edge detect- ed on the error comparator). dac inputs (d0?6) the digital-to-analog converter (dac) programs theoutput voltage using the d0Cd6 inputs. d0Cd6 are low- voltage (1.0v) logic inputs designed to interface direct- ly with the cpu. do not leave d0Cd6 unconnected. changing d0Cd6 initiates a transition to a new output- voltage level. change d0Cd6 together, avoiding greater than 20ns skew between bits. otherwise, incor- rect dac readings can cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall tran- sition time. the available dac codes and resulting out- put voltages are compatible with the intel imvp-6.5/ gmch specifications (table 2). ig v v fb m fb csp csn = () () vv r i out target fb fb = vv vv target fb dac gnds == + downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 26 ______________________________________________________________________________________ d6 d5 d4 d3 d2 d1 d0 imvp-6.5 output voltage (v) d6 d5 d4 d3 d2 d1 d0 imvp-6.5 output voltage (v) 0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.7000 0 0 0 0 0 0 1 1.4875 1 0 0 0 0 0 1 0.6875 0 0 0 0 0 1 0 1.4750 1 0 0 0 0 1 0 0.6750 0 0 0 0 0 1 1 1.4625 1 0 0 0 0 1 1 0.6625 0 0 0 0 1 0 0 1.4500 1 0 0 0 1 0 0 0.6500 0 0 0 0 1 0 1 1.4375 1 0 0 0 1 0 1 0.6375 0 0 0 0 1 1 0 1.4250 1 0 0 0 1 1 0 0.6250 0 0 0 0 1 1 1 1.4125 1 0 0 0 1 1 1 0.6125 0 0 0 1 0 0 0 1.4000 1 0 0 1 0 0 0 0.6000 0 0 0 1 0 0 1 1.3875 1 0 0 1 0 0 1 0.5875 0 0 0 1 0 1 0 1.3750 1 0 0 1 0 1 0 0.5750 0 0 0 1 0 1 1 1.3625 1 0 0 1 0 1 1 0.5625 0 0 0 1 1 0 0 1.3500 1 0 0 1 1 0 0 0.5500 0 0 0 1 1 0 1 1.3375 1 0 0 1 1 0 1 0.5375 0 0 0 1 1 1 0 1.3250 1 0 0 1 1 1 0 0.5250 0 0 0 1 1 1 1 1.3125 1 0 0 1 1 1 1 0.5125 0 0 1 0 0 0 0 1.3000 1 0 1 0 0 0 0 0.5000 0 0 1 0 0 0 1 1.2875 1 0 1 0 0 0 1 0.4875 0 0 1 0 0 1 0 1.2750 1 0 1 0 0 1 0 0.4750 0 0 1 0 0 1 1 1.2625 1 0 1 0 0 1 1 0.4625 0 0 1 0 1 0 0 1.2500 1 0 1 0 1 0 0 0.4500 0 0 1 0 1 0 1 1.2375 1 0 1 0 1 0 1 0.4375 0 0 1 0 1 1 0 1.2250 1 0 1 0 1 1 0 0.4250 0 0 1 0 1 1 1 1.2125 1 0 1 0 1 1 1 0.4125 0 0 1 1 0 0 0 1.2000 1 0 1 1 0 0 0 0.4000 0 0 1 1 0 0 1 1.1875 1 0 1 1 0 0 1 0.3875 0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750 0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625 0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500 0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375 0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.3250 0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125 0 1 0 0 0 0 0 1.1000 1 1 0 0 0 0 0 0.3000 0 1 0 0 0 0 1 1.0875 1 1 0 0 0 0 1 0.2875 0 1 0 0 0 1 0 1.0750 1 1 0 0 0 1 0 0.2750 0 1 0 0 0 1 1 1.0625 1 1 0 0 0 1 1 0.2625 0 1 0 0 1 0 0 1.0500 1 1 0 0 1 0 0 0.2500 0 1 0 0 1 0 1 1.0375 1 1 0 0 1 0 1 0.2375 table 2. imvp-6.5 output voltage vid dac codes downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 27 output-voltage transition timing the max17528 perform mode transitions in a controlledmanner, automatically minimizing input surge currents. this feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. at the beginning of an output-voltage transition, the max17528 blanks both pwrgd thresholds, preventing the pwrgd open-drain output and the clken open- drain output from changing states during the transition.the controllers reenable the lower pwrgd threshold approximately 20s after the slew-rate controller reach-es the target output voltage. the controllers reenable the upper pwrgd threshold 20s after the slew-rate controllers reach the target output voltage only for upward vid transitions. for downward vid transitions, the max17528 must also detect an error amplifier tran- sition (feedback drops below the new target threshold) before reenabling the upper pwrgd transition to avoid false pwrgd errors under pulse-skipping conditions. the slew rate (set by resistor r time ) must be set fast enough to ensure that the transition can be completedwithin the maximum allotted time. d6 d5 d4 d3 d2 d1 d0 imvp-6.5 output voltage (v) d6 d5 d4 d3 d2 d1 d0 imvp-6.5 output voltage (v) 0 1 0 0 1 1 0 1.0250 1 1 0 0 1 1 0 0.2250 0 1 0 0 1 1 1 1.0125 1 1 0 0 1 1 1 0.2125 0 1 0 1 0 0 0 1.0000 1 1 0 1 0 0 0 0.2000 0 1 0 1 0 0 1 0.9875 1 1 0 1 0 0 1 0.1875 0 1 0 1 0 1 0 0.9750 1 1 0 1 0 1 0 0.1750 0 1 0 1 0 1 1 0.9625 1 1 0 1 0 1 1 0.1625 0 1 0 1 1 0 0 0.9500 1 1 0 1 1 0 0 0.1500 0 1 0 1 1 0 1 0.9375 1 1 0 1 1 0 1 0.1375 0 1 0 1 1 1 0 0.9250 1 1 0 1 1 1 0 0.1250 0 1 0 1 1 1 1 0.9125 1 1 0 1 1 1 1 0.1125 0 1 1 0 0 0 0 0.9000 1 1 1 0 0 0 0 0.1000 0 1 1 0 0 0 1 0.8875 1 1 1 0 0 0 1 0.0875 0 1 1 0 0 1 0 0.8750 1 1 1 0 0 1 0 0.0750 0 1 1 0 0 1 1 0.8625 1 1 1 0 0 1 1 0.0625 0 1 1 0 1 0 0 0.8500 1 1 1 0 1 0 0 0.0500 0 1 1 0 1 0 1 0.8375 1 1 1 0 1 0 1 0.0375 0 1 1 0 1 1 0 0.8250 1 1 1 0 1 1 0 0.0250 0 1 1 0 1 1 1 0.8125 1 1 1 0 1 1 1 0.0125 0 1 1 1 0 0 0 0.8000 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0.7875 1 1 1 1 0 0 1 0 0 1 1 1 0 1 0 0.7750 1 1 1 1 0 1 0 0 0 1 1 1 0 1 1 0.7625 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0.7500 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0.7375 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 0.7250 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0.7125 1 1 1 1 1 1 1 0 table 2. imvp-6.5 output voltage vid dac codes (continued) downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 28 ______________________________________________________________________________________ the max17528 automatically controls the current to theminimum level required to complete the transition in the calculated time. the slew-rate controller uses an inter- nal capacitor and current-source programmed by r time to transition the output voltage. the total transi- tion time depends on r time , the voltage difference, and the accuracy of the slew-rate controller (c slew accuracy). the slew rate is not dependent on the totaloutput capacitance, as long as the surge current is less than the current limit. for all dynamic vid transitions, the transition time (t tran ) is given by: where dv target /dt = 12.5mv/s x 71.5k ? /r time is the slew rate, v old is the original output voltage, and v new is the new target voltage. see time slew-rate accuracy in the electrical characteristics table for slew-rate limits. for soft-start and shutdown, the con-troller automatically reduces the slew rate to 1/8. the output voltage tracks the slewed target voltage, making the transitions relatively smooth. excluding the load current, the average inductor current required to make an output voltage transition is: where dv target /dt is the required slew rate and c out is the total output capacitance. imvp-6.5 low-power sleep transition the imvp-6.5 cpu enters a low-power state to con-serve power (figure 5). the processor enters this state by initially setting the core voltage to the lfm voltage level (no lsb stepping). upon reaching the lfm volt- age level, the processor asserts dprlpvr, which is connected to skip as shown in figure 1, signaling that a very low current state has been entered. however, the processor can still lower the core voltage by lsb increments to further reduce power consumption under this very low-power sleep state. the processor exits the sleep state by pulling dprslvpr low and ramping up the core voltage by lsb increments. during all vid transitions, the max17528 blanks pwrgd (forced high impedance) and clken (forced low) until 20s after the internal target (which moves at the slew rate set byr time ) reaches the selected vid code. i c dv dt l out target ? () / t vv dv dt tran new old target = () / hfm vid lfm vid blank high impedance blank high impedance dprslpvr pwrgd t blank 20 s typ t blank 20 s typ dh cpu core voltage 1-phase forced pwm vid (d0?d6) active vid lfm vid pulse skipping hfm vid note: dprslpvr = skip. blank low blank low clken possible vid change figure 5. imvp-6.5 sleep transition downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 29 blank high impedance blank high impedance gfxdprslpvr pwrgd t blank 20 s typ t blank 20 s typ dh cpu core voltage 1-phase forced pwm vid (d0?6) active vid dprslp vid pulse skipping active vid note: gfxdprslpvr = skip = slow. deeper sleep vid figure 6. slow render gmch sleep transition gmch sleep transition for gmch applications ( clken = gnd), the system enters the sleep state by stepping the vid code down tothe deeper sleep vid code. during these vid transitions, the max17528 blanks pwrgd (forced high impedance) until 20s after the last vid transition is completed. upon reaching the low-voltage code, the system asserts gfxdprslpvr, which is connected to the max17528 skip and slow pins as shown in figure 2, allowing the voltage regulator to enter a pulse-skipping mode (forbest light-load efficiency). slow gmch sleep exit: to avoid audible noise, the sys- tem reduces the exit slew rate to minimize surge cur- rents from the input capacitors to the output capacitors. the exit transition begins by pulling gfxdprslpvrlow, followed by lsb vid steps every 2.5s until the active vid target is reached (figure 6). fast gmch sleep exit: when quickly exiting from the sleep state, the system immediately changes the vid code to the active vid code (no lsb stepping) and keeps gfxdprslpvr asserted to select the fast 10mv/s slew rate. upon completion of the transition, the system pulls gfxdprslpvr low to signal the beginning of active state operation. during all vid transitions, the max17528 blanks pwrgd (forced high impedance) until 20s after the internal target (which moves at the slew rate set by r time ) reaches the selected vid code. downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 30 ______________________________________________________________________________________ forced-pwm operation (normal mode) during soft-shutdown and normal operationwhen thecpu is actively running (skip = low, table 3), the max17528 operates with the low-noise, forced-pwm control scheme. forced-pwm operation disables the zero-crossing comparator, forcing the low-side gate- drive waveforms to constantly be the complement of the high-side gate-drive waveforms. this keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. forced-pwm operation comes at a cost: the no-load +5v bias supply current remains between 10ma to 50ma, depending on the external mosfets and switch- ing frequency. to maintain high efficiency under light- load conditions, the processor can switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. the max17528 automatically uses pulse-skipping operation during soft-start, regard- less of the skip configuration. light-load pulse-skipping operation during soft-start and sleep statesskip is pulledhighthe max17528 operates in pulse-skipping mode. the pulse-skipping mode enables the drivers zero- crossing comparator, so the controller pulls dl low when the low-side mosfet voltage drop (lx to gnd voltage) detects zero inductor current. this keeps the inductor from sinking current and discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. upon entering pulse-skipping operation, the controller temporarily blanks the upper pwrgd and clken thresholds, when the transition to pulse-skipping opera-tion coincides with a vid code change. once the error amplifier detects that the output voltage is in regulation, the upper pwrgd and upper clken , resume tracking the selected vid dac code. the max17528 automati-cally uses forced-pwm operation during soft-shutdown, regardless of the skip configuration. blank high impedance blank high impedance gfxdprslpvr pwrgd t blank 20 s typ t blank 20 s typ dh cpu core voltage 1-phase forced pwm vid (d0?d6) active vid dprslp vid pulse skipping active vid note: gfxdprslpvr = skip = slow. deeper sleep vid 10mv/ s figure 7. fast render gmch sleep transition downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 31 automatic pulse-skipping switchover in skip mode (skip = high), an inherent automaticswitchover to pfm takes place at light loads (figure 8). this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. the zero-crossing comparator senses the inductor current across the low-side mosfets. once v lx drops below the zero-crossing comparator threshold (see the electrical characteristics table), the comparator forces dl low (figure 3). this mechanism causes thethreshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current opera- tion. the pfm/pwm crossover occurs when the load-cur- rent is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 8). for a battery input range of 7v to 20v, this threshold is relative- ly constant, with only a minor dependence on the input voltage due to the typically low duty cycles. the total load current at the pfm/pwm crossover threshold (i load(skip) ) is approximately: the switching waveforms might appear noisy and asyn-chronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs between pfm noise and light-load efficiency are made by varying the inductor value. generally, low inductor val- ues produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size anddegraded load-transient response, especially at low input-voltage levels. power-up sequence (por, uvlo) the max17528 is enabled when shdn is driven high (figures 9 and 10). the internal reference powers upfirst, followed by the analog control circuitry. roughly 50s after the analog control circuitry powers up, the pwm controller is enabled and begins the soft-start sequence. power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar-ing the controller for operation. the v cc uvlo circuitry inhibits switching until v cc rises above 4.25v. the con- troller powers up the reference once the systemenables the controller, v cc is above 4.25v, and shdn is driven high. the soft-start sequence ramps the out-put voltage up to the target voltageeither the 1.1v boot voltage for imvp-6.5 ( clken pullup to 3.3v with 1.9k ? ) or the selected vid voltage for gmch ( clken = gnd)at 1/8 the nominal slew rate set by r time : where dv target /dt = 12.5mv/s x 71.5k ? /r time is the nominal slew rate. the soft-start circuitry does not use avariable current limit, so full output current is available immediately. the max17528 automatically uses pulse- skipping mode during soft-start and uses forced-pwm mode during soft-shutdown, regardless of the skip configuration. for imvp-6.5 applications ( clken pullup to 3.3v with 1.9k ? ), the max17528 pulls clken low approximately 60s after reaching pgdin is pulled high and the con-troller reaches the 1.1v boot voltage. at the same time, the max17528 slews the output to the selected vid voltage at the programmed nominal slew rate. pwrgd becomes high impedance approximately 5ms after clken is pulled low. for gmch applications ( clken = gnd), pwrgd becomes high impedance approximately 60s afterreaching the selected vid voltage. for automatic startup, the battery voltage should be present before v cc rises above its uvlo threshold. if the controller attempts to bring the output into regula-tion without the battery voltage present, the output undervoltage fault latch disables the controller. the max17528 remains shut down until the fault latch is cleared by toggling shdn or cycling the v cc power supply below 0.5v. t v dv dt tran start start target () / = () 8 i tv l vv v load skip sw out in out in () = ? ? ? ? ? ? ? ? ? ? ? ? inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out ? i ? t = figure 8. pulse-skipping/discontinuous crossover point downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 32 ______________________________________________________________________________________ shdn pwrgd v cc soft-start 1/8 r time slew rate soft-shutdown 1/8 r time slew rate clken vid (d0?6) valid vid invalid vid cpu core voltage internal pwm mode forced-pwm mode pulse skipping invalid vid 1.1v boot t blank 20 s typ t blank 60 s typ t blank 5ms typ t blank 60 s typ note: pgdin = v cc . figure 9. imvp-6.5 power-up and shutdown sequence timing diagram if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage to makevalid decisions. to protect the output from overvoltage faults, the controller shuts down immediately and forcesa high-impedance output (dl and dh pulled low) and pulls csn low through a 10 ? discharge mosfet. shdn pwrgd v cc soft-start 1/8 r time slew rate soft-shutdown 1/8 r time slew rate vid (d0?6) valid vid gmch core voltage internal pwm mode forced-pwm pulse skipping invalid vid t blank 5ms typ t blank 60 s typ figure 10. gmch power-up and shutdown sequence timing diagram downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 33 shdn slow skip operating mode gnd x x disabled low-power shutdown. dl forced low, and the controller is disab led. the supply current drops below 30a. rising x x pulse skipping 1/8 r time slew rate startup. when shdn is pulled high, the max17528 begins the startup sequence after the internal circuitry powers up. the max17528 enab les the pwm controller and ramps the output voltage up to the startup voltage. see figures 9 and 10. high x low forced-pwm nominal r time slew rate full power. the no-load output voltage is determined by the selected vid dac code (table 2). high high high pulse-skipping nominal r time slew rate low-power mode (nominal transition). the no-load output voltage is determined by the selected vid dac code (table 2). when skip is pulled high, the controller immediately enters pulse-skipping operation, allowi ng automatic pwm/pfm switchover under light loads. the pwrgd and clken upper thresholds are blanked during the transition. high low high pulse-skipping 1/2 r time slew rate low-power mode (slow transition). the no-load output voltage is determined by the selected vid dac code (table 2). when skip is pulled high, the max17528 enters pulse-skipping operation, allowing automatic pw m/pfm switchover under light loads. the pwrgd and clken thresholds are blanked during the transition. falling x x forced-pwm 1/8 r time slew rate shutdown. when shdn is pulled low, the max17528 immediately pulls pwrgd low, clken becomes high impedance, and the output voltage is ramped down to ground. once the output rea ches zero, the controller enters the low-power shutdown state. see figures 9 and 10. high x x disabled fault mode. the fault latch has been set by the max17528 uvp fault, r ton open fault, or thermal-shutdown protection. the controller remains in fault mode until v cc power is cycled or shdn toggled. table 3. operating mode truth table shutdown when shdn goes low, the max17528 enters low- power shutdown mode. pwrgd is pulled low immedi-ately, and the output voltage ramps down at 1/8 the slew rate set by r time : where dv target /dt = 12.5mv/s x 71.5k ? /r time is the nominal slew rate. slowly discharging the output capaci-tors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side mosfet (underdamped response). this eliminates the need for the schottky diode connected between the output and ground to clamp the negative output-voltage excursion. after the controller reaches the zero target, the max17528 shuts down completely the drivers are disabled (dl and dh are pulled low)the internal reference turns off, and the supply currents drop to about 30a (max). when an output undervoltage fault condition activates the shutdown sequence, the protection circuitry sets the uvp fault latch to prevent the controller from restarting. to clear the fault latch and reactivate the controller, toggle shdn or cycle v cc power below 0.5v. current monitor (imon) the max17528 includes a unidirectional transconduc-tance amplifier that sources current proportional to the positive current-sense voltage. the imon output cur- rent is defined by: i imon = g m(imon) x (v csp - v csn ) where g m(imon) = 5ms (typ) and the imon current is unidirectional (sources current out of imon only) forpositive current-sense values. for negative current- sense voltages, the imon current is zero. t v dv dt tran shdn out target () / = () 8 downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 34 ______________________________________________________________________________________ the current monitor allows the processor to accuratelymonitor the cpu load and quickly calculate the power dissipation to determine if the system is about to over- heat before the significantly slower temperature sensor signals an overtemperature alert. connect an external resistor between imon and vss_sense to create the desired imon gain based on the following equation: r imon = 0.999v/(imax x r sense x g m(imon) ) where imax is defined in the current monitor section ofthe intel imvp-6.5 specification and based on discrete increments (10a, 20a, 30a, 40a, etc.,), r sense is the typical effective value of the current-sense element(sense resistor or inductor dcr) that is used to provide the current-sense voltage, and g m(imon) is the typical transconductance amplifier gain as defined in the electrical characteristics table. the imon voltage is internally clamped to a maximumof 1.1v (typ), preventing the imon output from exceed- ing the imon voltage rating even under overload or short-circuit conditions. when the controller is disabled, imon is pulled to ground. the transconductance amplifier and voltage clamp are internally compensated, so imon cannot directly drive large capacitance values. to filter the imon signal, use an rc filter as shown in figure 1. temperature comparator ( vrhot ) the max17528 also features an independent compara-tor with an accurate threshold that tracks the analog supply voltage (v hot = 0.3 x v cc ). this makes the ther- mal trip threshold independent of the v cc supply volt- age tolerance. use a resistor- and thermistor-dividerbetween v cc and gnd to generate a voltage-regulator overtemperature monitor. place the thermistor as closeas possible to the mosfets and inductors. output undervoltage (uvp) protection the output uvp function limits the power loss by dis-abling the regulator if the max17528 output voltage drops 400mv below the target voltage; the controller activates the shutdown sequence and sets the fault latch. once the controller ramps down to zero, it forces dl high and dh low. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch andreactivate the controller. uvp protection can be disabled through the no-fault test mode (see the no-fault test mode section). thermal fault protection the max17528 features a thermal-fault-protection cir-cuit. when the junction temperature rises above +160c, a thermal sensor sets the fault latch, forces dl low, and pulls dh low. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch andreactivate the controller after the junction temperature cools by 15c. thermal shutdown can be disabled through the no-fault test mode (see the no-fault test mode section). no-fault test mode the latched fault-protection feature can complicate theprocess of debugging prototype breadboards since there are (at most) a few milliseconds in which to deter- mine what went wrong. therefore, a no-fault test mode is provided to disable the fault protectionuvp, thermal shutdown, and ton open-circuit fault protec- tion. the no-fault test mode also disables the bst switch, although the switchs body diode provides suffi- cient power for the high-side driver to function properly. additionally, the test mode clears the fault latch if it has been set. the no-fault test mode is entered by forcing 11v to 13v on shdn . mosfet gate drivers the dh and dl drivers are optimized for driving mod-erate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh) source and sink 2.2a, and the low-side gate drivers(dl) source 2.7a and sink 8a. this ensures robust gate drive for high-current applications. the dh high-side mosfet driver is powered by an internal charge-pump boost switch at bst, while the dl synchronous-rectifier driver is powered directly by the 5v bias supply (v dd ). adaptive dead-time circuits monitor the dl and dh dri-vers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates for the adaptive dead-time circuits to work properly; other- wise, the sense circuitry in the max17528 interprets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 35 the internal pulldown transistor that drives dl low isrobust, with a 0.25 ? (typ) on-resistance. this helps pre- vent dl from being pulled up due to capacitive couplingfrom the drain to the gate of the low-side mosfets when the inductor node (lx) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces must guarantee rising lxedges do not pull up the low-side mosfets gate, caus- ing shoot-through currents. the capacitive coupling between lx and dl created by the mosfets gate-to- drain capacitance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following minimum threshold:typically, adding a 4700pf between dl and power ground (c nl in figure 11), close to the low-side mosfets, greatly reduces coupling. do not exceed22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, shoot-through currents can be caused by a combination of fast high-side mosfets and slow low- side mosfets. if the turn-off delay time of the low-side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 ? in series with bst slows down the high-side mosfet turn-on time, elimi-nating the shoot-through currents without degrading the turn-off time (r bst in figure 11). slowing down the high-side mosfet also reduces the lx node rise time,thereby reducing emi and high-frequency coupling responsible for switching noise. quick-pwm design procedure firmly establish the input voltage range and maximumload current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing five factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage afterdrops due to connectors, fuses, and battery selec- tor switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) determines the instantaneous component stressesand filtering requirements, and thus, drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal stresses, and thus, drives the selection of inputcapacitors, mosfets, and other critical heat-con- tributing components. modern notebook cpus gen- erally exhibit i load = i load(max) x 80%. load line (voltage positioning): the load line (out- put voltage vs. load slope) dynamically lowers theoutput voltage in response to the load current, reduc- ing the output capacitance requirement and the processors power dissipation. the intel specification clearly defines the load-line requirement in the power- supply specifications for each processor family. vv c c gs th in rss iss () < ? ? ? ? ? ? bst dh lx input (v in ) c bst c byp v dd (r bst )* (c nl )* n h l dl pgnd (r bst )* optional?he resistor lowers emi by decreasing the switching node rise time.(c nl )* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. n l max17528 figure 11. gate-drive circuit downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 36 ______________________________________________________________________________________ switching frequency: this choice determines the basic trade-off between size and efficiency. theoptimal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target due to rapidimprovements in mosfet technology that are mak- ing higher frequencies more practical. inductor operating point: this choice provides trade-offs between size vs. efficiency and transientresponse vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripplecurrent or lir) determine the inductor value as follows: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. molded cores are often the best choice, although powdered iron and ferrite cores are inexpensive and can work well at 300khz. the core must be large enough not to saturate at the peak inductor current (i peak ): transient response the inductor ripple current impacts transient-responseperformance, especially at low v in - v out differentials. low inductor values allow the inductor current to slewfaster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time. the worst-case output sag voltage can be determined by: where t off(min) is the minimum off-time (see the electrical characteristics table). the amount of overshoot due to stored inductor energycan be calculated as: current-limit and slew-rate control (time and ilim) time and ilim are used to control the slew rate andcurrent limit. time regulates to a fixed 2.0v. the max17528 uses the time source current to set the slew rate (dv target /dt). the higher the source current, the faster the nominal output-voltage slew rate:where r time is the sum of resistance values between time and ground.the ilim voltage determines the valley current-sense threshold. when ilim = v cc , the controller uses the preset 22.5mv (typ) current-limit threshold. in anadjustable design, ilim is connected to a resistive volt- age-divider connected between time and ground. the differential voltage between time and ilim sets the current-limit threshold (v limit ), so the valley current- sense threshold is:where the v limit tolerances are defined in the electrical characteristics table. this allows design flexibility since the dcr sense cir-cuit or sense resistor does not have to be adjusted to meet the current limit as long as the current-sense volt- age never exceeds 50mv. keeping v limit between 20mv to 40mv leaves room for future current-limitadjustment. v vv limit time ilim = 10 dv dt mv s k r target time /./ . = ? ? ? ? ? ? 12 5 71 5 ? v il cv soar load max out out () ? () 2 2 v vt v t sag out sw in off = () ? ? ? ? ? ? + li load(max) 2 ? ( m min out out in out sw in cv vv t v ) ? ? ? ? ? ? () ? ? ? ? ? ? 2 tt off min () ? ? ? ? ? ? ? ? ii lir peak load max =+ ? ? ? ? ? ? () 1 2 l vv f i lir v v in out sw load max out in = ? ? ? ? ? ? ? ? ? ? ? ? () downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 37 the minimum current-limit threshold must be highenough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore:where: where r sense is the sensing resistor and r csp-csn / r lx-csn is the ratio of resistor-divider with dcr- sensing approach. voltage positioning and loop compensation voltage positioning dynamically lowers the output volt-age in response to the load current, reducing the out- put capacitance and processors power dissipation requirements. the controller uses a transconductance amplifier to set the transient and dc output voltage droop (figure 3) as a function of the load. this adjusta- bility allows flexibility in the selected current-sense resistor value or inductor dcr, and allows smaller cur- rent-sense resistance to be used, reducing the overall power dissipated. steady-state voltage positioning connect a resistor (r fb ) between fb and v out to set the dc steady-state droop (load line) based on therequired voltage-positioning slope (r droop ): where the effective current-sense resistance (r sense ) depends on the current-sense method (see the current sense section), and the voltage-positioning amplifiers transconductance (g m(fb) ) is typically 600s as defined in the electrical characteristics table. when the inductors dcr is used as the current-sense element(r sense = r dcr ), the current-sense design should include a thermistor to minimize the temperaturedependence of the voltage-positioning slope as shown in figure 1. output capacitor selection the output filter capacitor must have low enough effec-tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core converters and other applications where the output is subject to large-load transients, the outputcapacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tors esr. the maximum esr to meet ripple require- ments is: where f sw is the switching frequency. the actual capacitance value required relates to the physical sizeneeded to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usu- ally selected by esr and voltage rating rather than by capacitance value (this is true of polymer types). when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, onceenough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations for quick-pwm controllers, stability is determined bythe value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where: and: where c out is the total output capacitance, r esr is the total esr, r droop is the voltage-positioning slope, and rrr r eff esr droop pcb =+ + f rc esr eff out = 1 2 f f esr sw r vf l vv v v esr in sw in out out ripple () ? ? ? ? ? ? ? ? rr v i esr pcb step load max + () ? () r r rg fb droop sense m fb = () i v r v dcr r r valley limit sense limit csp csn lx csn == ii lir valley load max > ? ? ? ? ? ? () 1 2 downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 38 ______________________________________________________________________________________ r pcb is the parasitic board resistance between the out- put capacitors and sense resistors.for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors in widespread use at the time of publication have typical esr zero frequencies below 50khz. in the standard gmch application circuit, the esr needed to support a 10mv p-p ripple is 10mv/(10a x 0.3) = 3.3m ? . two 330f/2.5v panasonic sp (type sx) capacitors inparallel provide 3.0m ? (max) esr. with a 5m ? droop and 0.5m ? pcb resistance, the typical combined esr results in a zero at 28khz.ceramic capacitors have a high-esr zero frequency, but applications with significant voltage positioning can take advantage of their size and low esr. do not put high-value ceramic capacitors directly across the out- put without verifying that the circuit contains enough voltage positioning and series pcb resistance to ensure stability. when only using ceramic output capacitors, output overshoot (v soar ) typically deter- mines the minimum output capacitance requirement.their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load con- ditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. unstable operation manifests itself in two related, but distinctly different ways: double pulsing and feedback loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased out- put ripple. however, it can indicate the possible pres- ence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple currentrequirement (i rms ) imposed by the switching currents. the i rms requirements can be determined by the fol- lowing equation:the worst-case rms current requirement occurs when operating with v in = 2 x v out . at this point, the above equation simplifies to i rms = 0.5 x i load . for most applications, nontantalum chemistries (ceramic,aluminum, or os-con) are preferred due to their resis- tance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the quick-pwm controller is operated as the second stage of a two-stage power-conversion system, tanta- lum input capacitors are acceptable. in either configu- ration, choose an input capacitor that exhibits less than +10c temperature rise at the rms input current for optimal circuit longevity. power-mosfet selection most of the following mosfet guidelines focus on thechallenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at bothv in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurswhere the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possi- ble on-resistance (r ds(on) ), comes in a moderate- sized package (i.e., one or two 8-pin sos, dpak, ord 2 pak), and is reasonably priced. make sure that the dl gate driver can supply sufficient current to supportthe gate charge and the current injected into the para- sitic gate-to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction prob- lems can occur (see the mosfet gate drivers section). i i v vvv rms load in out in out = ? ? ? ? ? ? () downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers ______________________________________________________________________________________ 39 mosfet power dissipation worst-case conduction losses occur at the duty factorextremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at theminimum input voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfetcan be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issueuntil the input is greater than approximately 15v. calculating the power dissipation in high-side mosfet (n h ) due to switching losses is complicated since it must allow for difficult quantifying factors that influencethe turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold volt- age, source inductance, and pcb layout characteris- tics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c oss is the n h mosfets output capacitance, q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (2.2a typ).switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c x v in 2 x f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased fromv in(max) , consider choosing another mosfet with lower parasitic capacitance.for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage:the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) , but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro-tect against this possibility, you can over design the circuit to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including thresholdtolerance and on-resistance variation. the mosfets must have a good-size heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage low enough to prevent the low-side mosfet bodydiode from turning on during the dead time. select a diode that can handle the load current during the dead times. this diode is optional and can be removed if effi- ciency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements ofthe high-side mosfets. typically, 0.1f ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1f. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets gates: where n is the number of high-side mosfets used for one regulator, and q gate is the gate charge specified in the mosfets data sheet. for example, assume (2)irf7811w n-channel mosfets are used on the high side. according to the manufacturers data sheet, a sin- gle irf7811w has a maximum gate charge of 24nc (v gs = 5v). using the above equation, the required boost capacitance would be:selecting the closest standard value, this example requires a 0.22f ceramic capacitor. c nc mv f bst = = 224 200 024 . c nq mv bst gate = 200 ii i i load valley max inductor valley max =+ ? ? ? ? ? ? = () () ? 2 pd nl sistive v v ir out in max load ds on (re ) () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? () 1 2 pd nhswitching v i f q i cvf in max load sw gsw gate oss in sw () () () = ? ? ? ? ? ? + 2 2 pd nh sistive v v ir out in load ds on (re ) () = ? ? ? ? ? ? () 2 downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers 40 ______________________________________________________________________________________ applications information pcb layout guidelines careful pcb layout is critical to achieve low switchinglosses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board with their ground terminals flush against one another. follow the max17528 evaluation kit layout and use the following guidelines for good pcb layout: ? high-current path/components: keep the high-cur- rent paths short, especially at the ground terminals.this is essential for stable, jitter-free operation. ? keep the power traces and load connections short. this is essential for high efficiency. the use of thickcopper pcbs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance causes a measur- able efficiency penalty. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to bemade longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ? mosfet drivers: keep the high-current, gate-dri- ver traces (dl, dh, lx, and bst) short and wideto minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot- through currents. ? analog control signals: connect all analog grounds to a separate solid copper plane, which connects tothe gnd pin of the quick-pwm controller as shown in figures 1 and 2. this includes the v cc bypass capacitor, remote-sense bypass capacitors, andthe compensation (ccv) components. ? csp and csn connections for current limiting and voltage positioning must be made using kelvin-sense connections to guarantee the current-sense accuracy. ? route high-speed switching nodes (lx, dh, bst, and dl) away from sensitive analog areas (fb,csp, csn, ccv, etc.). layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl gate traces must be short andwide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic). 3) group the gate-drive components (bst capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in the standard application circuits. this dia-gram can be viewed as having three separate ground planes: input/output system ground, where all the high-power components go; the power ground plane, where the pgnd pin and v dd bypass capacitor go; and the controllers analogground plane where sensitive analog components, the analog gnd pin, and v cc bypass capacitor go. the analog gnd plane must meet the pgnd planeonly at a single point directly beneath the controller. this star ground point (where the power and analog grounds are connected) should connect to the high-power system ground with a low-impedance connection (short trace or multiple vias) from pgnd to the source of the low-side mosfet. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filtercapacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close as is practical to the cpu. downloaded from: http:///
max17528 1-phase quick-pwm intel imvp-6.5/gmch controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 41 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. chip information process: bicmos package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . package type package code document no. 32 tqfn t3255-3 21-0140 downloaded from: http:///

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